• High-Performance Static CMOS Technology
• TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
  • 24-MHz System Clock (48-MHz Pipeline Mode)
  • Independent 16/32-Bit Instruction Set
  • Open Architecture With Third-Party Support
  • Built-In Debug Module
  • Big-Endian Format Utilized
• Integrated Memory
  • 256K-Byte Program Flash
    • One Bank With 14 Contiguous Sectors
    • Internal State Machine for Programming and Erase
  • 12K-Byte Static RAM (SRAM)
• Operating Features
  • Core Supply Voltage (V_CC): 1.81 V-2.05 V
  • I/O Supply Voltage (V_CCIO): 3.0 V-3.6 V
  • Low-Power Modes: STANDBY and HALT
  • Extended Industrial Temperature Ranges
• 470+ System Module
  • 32-Bit Address Space Decoding
  • Bus Supervision for Memory and Peripherals
  • Analog Watchdog (AWD) Timer
  • Real-Time Interrupt (RTI)
  • System Integrity and Failure Detection
• Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler
  • Multiply-by-4 or -8Internal ZPLL Option
  • ZPLL Bypass Mode
• Six Communication Interfaces:
  • Two Serial Peripheral Interfaces (SPIs)
    • 255 Programmable Baud Rates
  • Two Serial Communications Interfaces (SCIs)
    • 2²⁴ Selectable Baud Rates
    • Asynchronous/Isosynchronous Modes
  • Standard CAN Controller (SCC)
    • 16-Mailbox Capacity
    • Fully Compliant With CAN Protocol, Version 2.0B
  • Class II Serial Interface (C2SIb)
    • Two Selectable Data Rates
    • Normal Mode 10.4 Kbps and 4X Mode 41.6 Kbps
• High-End Timer (HET)
  • 16 Programmable I/O Channels:
    • 14 High-Resolution Pins
    • 2 Standard-Resolution Pins
  • High-Resolution Share Feature (XOR)
  • High-End Timer RAM
    • 64-Instruction Capacity
• 10-Bit Multi-Buffered ADC (MibADC) 16-Channel
  • 64-Word FIFO Buffer
  • Single- or Continuous-Conversion Modes
  • 1.55 µs Minimum Sample and Conversion Time
  • Calibration Mode and Self-Test Features
• 8 External Interrupts
• Flexible Interrupt Handling
• 11 Dedicated GIO Pins, 1 Input-Only GIO Pin, and 38 Additional Peripheral I/Os (A256)
• External Clock Prescale (ECP) Module
  • Programmable Low-Frequency External Clock (CLK)
• Compatible ROM Device
• On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1 (JTAG) Test-Access Port⁽¹⁾
• 100-Pin Plastic Low-Profile Quad Flatpack (PZ Suffix)

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