• 32-bit ARM7TDMI-S™ RISC core, up to 50 MHz operating frequency
• Enhanced DMA with channel multiplexer
• 512 Kbyte program Flash EEPROM
• 32 Kbyte data Flash EEPROM
• 32 Kbyte RAM
• 16-bit external bus interface to support off-chip devices
• 16-channel, 10-bit analog-to-digital converter
• 16-channel enhanced modular I/O timer subsystem
• Four enhanced serial communications interfaces
• Four CAN 2.0 software compatible interfaces
• Two serial peripheral interfaces (SPI)
• One I²C bus interface
• 10-channel, 24-bit periodic interrupt timer
• 112 general purpose input/output port pins shared with peripherals, with optional wake-up interrupts and 3.3 V to 5 V input and drive capability
• Flexible interrupt controller
• JTAG test access port (TAP) and Embedded ICE debug interfaces, with real-time instruction trace support via Nexus Class 2 Plus interface
• On-chip clock generation with selectable standard or low-power Pierce oscillator driving a phase-locked loop clock frequency multiplier
• On-chip dual 2.5 V linear voltage regulator
• 144-pin LQFP package

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